The element separation of semiconductor integrated circuit devices has hitherto relied on a PN junction separation technique. As the element has been made finer with an increasing degree of integration, the technique has been changed to a oxide film separation technique (so-called iso-planer).
In recent years, however, since the fineness of the element further proceeds, there arises the necessity of reducing and area of the separation region to meet a high degree of integation. For meeting a high speed requirement, reduction of parasitic capacitance is necessary, thus making it essential to reduce an area in the element forming region.
Recently, there has been used a reactive ion etching (hereinafter referred to simply as R.I.E.) technique which is anisotropic etching technique of etching a film vertically with respect to a substrate surface. Thus, a new element separation technique has now been developed in place of the oxide film separation method.
Among hitherto proposed, new separation techniques, a technique to which attention has been paid and which has been attemped to be put in practice is a trench separation technique.
Specific examples of the trench separation technique include, for example, those set forth by H. Goto et al "A new isolation technology for bipolar VLSI logic (IOP-L)" 1985 VLSI Symposium, pp. 42-43, and Japanese Laid-open Patent Application Nos. 59-208744 and 61-264736.
Fundamental steps of the trench separation technique used in a known method of fabricating a semiconductor, integrated circuit device are described with reference to the step illustrative views shown in FIG. 2.
As shown in FIG. 2(A), a field silicon oxide film 202 is formed on an arbitrary region of a silicon substrate 201 according to a known selective oxidation method (LOCOS method).
Thereafter, according to the CVD method, a mask silicon oxide film 203 is formed, followed by forming an opening 205 at a region which serves as an element separation region, through a photoresist 204 by the use of a known photolithographic technique.
Subsequently, as shown in FIG. 2(B), the photoresist 204 is removed, after which the sillicon substrate 201 is substantially vertically etched through a mask of the mask silicon oxide film 203 according to R.I.E. to form grooves 206.
After removal of the mask silicon oxide film 203, an inner wall silicon oxide film 207 is formed on the entire surface according to a thermal oxidation method or the CVD method as shown in FIG. 2(C).
If necessary, the inner wall silicon oxide film 207 may be provided thereon with a oxidation-resestant silicon nitride film.
As shown in FIG. 2(D), a thick polysilicon 208 is deposited over the entire surface to completely fill up the grooves 206 therewith.
Finally, as shown in FIG. 2(E), the polysilicon layer 208 is etched back and planarized on the surface thereof. Thereafter, the polysilicon 208 is converted to a CAP silicon oxide film 209 on the surface thereof. The inner wall silicon oxide film 207 is removed from an element forming region 210 to complete the separation procedure.
In FIG. 4, there are shown sectional views after completion of the separation steps of the oxide film separation method and the trench separation method, respectively.
FIG. 4(A) is a sectional view showing the separation with an oxide film, in which indicated at 401 is a field oxide film, at 402 is an element forming region, at 403 is an N.sup.+ diffusion layer, at 404 is a P.sup.+ diffusion layer and at 405 is a substrate.
FIG. 4(B) shows the separation by the trench separation method wherein indicated at 406 is a field oxide film, at 407 an element forming region, at 408 is an N.sup.+ diffusion layer, at 409 is a P.sup.+ diffusion layer, at 410 is a substrate and at 411 is a trench.
In the oxide film separation method shown in FIG. 4(A), the N.sup.+ diffusion layer 403 serving for diffusion by burying and the P.sup.+ diffusion layer 404 serving as a channel stopper are directly contacted with each other, so that the junction capacitance therebetween becomes great. On the contrary, in the trench separation method shown in FIG. 4(B), the trench 411 is formed substantially in a vertical direction relative to the silicon substrate 410 by R.I.E. in such a way that it passes from the field oxide film 406 through the N.sup.+ buried diffusion layer to a deep region.
More particularly, the N.sup.+ diffusion layer 408 and the P.sup.+ diffusion layer 409 are not directly contacted.
Accordingly, the junction capacitance which is taken into account is only one between the N.sup.+ diffusion layer 408 serving as a buried diffusion layer and the substrate 410.
When comparing with the oxide film separation method, the capacitance lowers remarkably. This will result in a drastic improvement in the high speed performance.
According to the above method, such a structure is obtained wherein part of the field silicon oxide film 302 is sandwiched between the element forming region 301 and the trench 303 as shown in FIG. 3(A).
For further high speed performance, the reduction in capacitance between the collector-substrate will become more important. It is considered ideal to provide a structure, as shown in FIG. 3(B), wherein the element forming region 301 and the trench 303 are in direct contact with each other.
However, the position of the trench 303 is determined by mask alignment and consideration should be given to any shift in the mask alignment, forcing the structure shown in FIG. 3(A). More particularly, if the mask alignment is not allowed but where shifted, the silicon surface is exposed aside from the element forming region 301 as shown in FIG. 3(C), with an attendant problem that short circuiting between the wiring metal layer and the substrate takes place.
If the field silicon oxide film 302 and the trench 303 are formed in an order reverse to currently employed order, the structure of FIG. 3(B) may be formed. In this case, oxidation will proceed in a vertical direction along the side wall oxide film which is formed at the side wall of the trench 303, thus presenting the problem of causing crystal defects to be produced owing to an increase of the volume.
The present invention provides a method for fabricating a semiconductor integrated circuit device which can solve, among the prior art problems, the problem of the short circuiting between the wiring metal layer and the substrate and the problem of producing crystal defects owing to an increase of the volume.